Dual gate integrated circuits having both high voltage devices, which may also be referred to herein as input/output (I/O) devices, and low voltage, or core, devices have gained wide acceptance and utility in the semiconductor industry since their introduction. Because of the different operating voltages associated with the core device versus the I/O device, the gate oxide for the lower voltage core device is much thinner than the gate oxide for the higher voltage I/O device. For example, the thickness of the gate oxide for the core device may range from about 0.7 nm to about 2 nm, while the thickness of the gate oxide for the I/O device may range from about 2.5 nm to about 8 nm.
Conventional processes have, therefore, required manufactures to proceed through a number of mask, etch and clean steps to achieve these different gate oxide thicknesses. In a typical process, the thicker I/O gate oxide is produced by first growing the desired thickness of oxide over the surface of the wafer. The desired I/O areas are then protected using well known masking and photolithographic processes. The oxide that is not protected by the mask is removed with conventional etch processes, after which the mask is removed. The appropriate clean steps are then conducted, and the wafer is subjected to a second, carefully controlled oxidation process to grow the thinner gate oxide for the core devices.
These conventional processes do achieve the desired thicknesses for the different devices. Unfortunately, however, the grow, mask, etch, clean and re-grow steps potentially damage the silicon surface that can lead to leakage at the interface of the silicon and the gate oxide. This leakage is undesirable, particularly in the low voltage or core devices. In addition, these multiple process steps introduces manufacturing complexity in that more variables are introduced into a process in which hundreds of variables already exist.
To avoid these additional process steps, manufactures turned to conducting a high dose nitrogen implant in the core device areas. In this process, the I/O device areas are masked off, and a high dose of nitrogen is implanted into the low voltage core device areas. Upon completion of the nitrogen implant, the mask is removed and the wafer is subjected to an oxidizing environment. The result is that the respective target thicknesses for each of the device areas are achieved without the additional process steps. Unfortunately, however, manufacturers have become reluctant to use this high dose nitrogen implant because it has been found to damage the silicon surface, which can also lead to leakage within the device.
Accordingly, what is needed in the art is a method of manufacturing an integrated circuit that overcomes the disadvantages associated with the prior art process discussed above.